Writing Testbenches: Functional Verification of HDL Models

By:

Janick Bergeron

Format:

Hardback

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Description

This second edition presents the most up-to-date verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems. Topics included are: discussions on openvera and e; approaches for writing constrainable random stimulus generators; strategies for making testbenches self-checking; a clear blueprint of a verification process that aims for first time success; recent advances in functional verification such as coverage-driven verification process; VHDL and Verilog language semantics; the semantics are presented in new verification-oriented languages; techniques for applying stimulus and monitoring the response of a design; behavioural modelling using non-synthesizeable constructs and coding style; and updated for Verilog 2001.

Release date NZ

February 28th, 2003

Author

Janick Bergeron

Audiences

Postgraduate, Research & Scholarly
Professional & Vocational
Undergraduate

Edition

2nd ed. 2003

Illustrations

XXX, 478 p.

Pages

478

Dimensions

155x235x28

ISBN-13

9781402074011

Product ID

2052941

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