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Self-Checking and Fault-Tolerant Digital Design on Hardback by Parag K Lala
Self-Checking and Fault-Tolerant Digital Design on Hardback by Parag K Lala
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Self-Checking and Fault-Tolerant Digital Design

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Description

With VLSI chip transistors getting smaller and smaller, today's digital systems are more complex than ever before. This increased complexity leads to more cross-talk, noise, and other sources of transient errors during normal operation. Traditional off-line testing strategies cannot guarantee detection of these transient faults. And with critical applications relying on faster, more powerful chips, fault-tolerant, self-checking mechanisms must be built in to assure reliable operation. Self-Checking and Fault-Tolerant Digital Design deals extensively with self-checking design techniques and is the only book that emphasizes major techniques for hardware fault tolerance. Graduate students in VLSI design courses as well as practicing designers will appreciate this balanced treatment of the concepts and theory underlying fault tolerance along with the practical techniques used to create fault-tolerant systems.

Author Biography:

The author is currently a Professor in the Department of Electrical Engineering at North Carolina A&T State University. He is the author of more than 75 papers, and three books published by Prentice Hall. His research interests include design for testability, self-checking logic design, automatic logic synthesis of low power logic circuits, andCPLD/FPGA based system design. He received a M.S. from King's College, London, and a Ph.D. from the City University of London.
Release date NZ
July 24th, 2000
Author
Audience
  • Professional & Vocational
Country of Publication
United States
Imprint
Morgan Kaufmann Publishers In
Pages
400
Publisher
Elsevier Science & Technology
Dimensions
187x235x14
ISBN-13
9780124343702
Product ID
2624936

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