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Parallel Computer Organization and Design on Hardback by Michel Dubois
Parallel Computer Organization and Design on Hardback by Michel Dubois
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Parallel Computer Organization and Design

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Description

Teaching fundamental design concepts and the challenges of emerging technology, this textbook prepares students for a career designing the computer systems of the future. In-depth coverage of complexity, power, reliability and performance, coupled with treatment of parallelism at all levels, including ILP and TLP, provides the state-of-the-art training that students need. The whole gamut of parallel architecture design options is explained, from core microarchitecture to chip multiprocessors to large-scale multiprocessor systems. All the chapters are self-contained, yet concise enough that the material can be taught in a single semester, making it perfect for use in senior undergraduate and graduate computer architecture courses. The book is also teeming with practical examples to aid the learning process, showing concrete applications of definitions. With simple models and codes used throughout, all material is made open to a broad range of computer engineering/science students with only a basic knowledge of hardware and software.

Author Biography:

Michel Dubois is a Professor in the Ming Hsieh Department of Electrical Engineering at the University of Southern California (USC) and part of the Computer Engineering Directorate. Before joining USC in 1984, he was a research engineer at the Central Research Laboratory of Thomson-CSF in Orsay, France. He has published more than 150 technical papers on computer architecture and edited two books. He is a Fellow of the IEEE and of the ACM. Murali Annavaram is an Assistant Professor and Robert G. and Mary G. Lane Early Career Chair in the Ming Hsieh Department of Electrical Engineering at the University of Southern California, and part of the Computer Engineering Directorate, where he has developed and taught advanced computer architecture courses. Prior to USC, he spent six years at Intel researching various aspects of future CMP designs. Per Stenström is a Professor of Computer Engineering at Chalmers University of Technology, Sweden. He has published two textbooks and over 100 technical papers. He has been a visiting scientist at Carnegie-Mellon University, Stanford University and the University of Southern California, and also was engaged in research at Sun Microsystems on its chip-multithreading technology. He is a Fellow of the IEEE and of the ACM and is a member of the Royal Swedish Academy of Engineering Sciences and the Academia Europaea.
Release date NZ
August 30th, 2012
Audiences
  • Professional & Vocational
  • Tertiary Education (US: College)
Illustrations
Worked examples or Exercises; 49 Tables, black and white; 206 Line drawings, unspecified
Pages
562
Dimensions
192x252x29
ISBN-13
9780521886758
Product ID
18394598

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