This book summarizes the recent breakthroughs in hardware implementation of neuro-inspired computing using resistive synaptic devices. The authors describe how two-terminal solid-state resistive memories can emulate synaptic weights in a neural network. Readers will benefit from state-of-the-art summaries of resistive synaptic devices, from the individual cell characteristics to the large-scale array integration. This book also discusses peripheral neuron circuits design challenges and design strategies. Finally, the authors describe the impact of device non-ideal properties (e.g. noise, variation, yield) and their impact on the learning performance at the system-level, using a device-algorithm co-design methodology.
Shimeng Yu He received the B.S. degree in microelectronics from Peking University, Beijing, China, in 2009 and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University, Stanford, CA, USA, in 2011 and in 2013, respectively. He joined Arizona State University, Tempe, AZ, USA, as an assistant professor of electrical engineering and computer engineering in 2013.
His research interests are emerging nano-devices and circuits with a focus on the resistive memories for different applications including neuro-inspired computing, monolithic 3D integration, hardware security, radiation-hard electronics, etc. He has published more than 50 journal papers and more than 90 conference papers with citations of more than 4000 and H-index of 28 according to Google Scholar.
Among his honors, he is a recipient of the Stanford Graduate Fellowship from 2009 to 2012, the IEEE Electron Devices Society Masters Student Fellowship in 2010, the IEEE Electron Devices Society Ph.D. Student Fellowship in 2012, the DOD-DTRA Young Investigator Award in 2015, and the NSF Faculty Early CAREER Award in 2016 on the topic of scaling up resistive synaptic arrays for neuro-inspired computing.
He did summer internship in IMEC, Belgium, in 2011 and the IBM TJ Watson Research Center in 2012. He held visiting faculty position in the Air Force Research Laboratory in 2016. He has been serving the Technical Committee of Nanoelectronics and Gigascale Systems, IEEE Circuits and Systems Society, since 2014.