Introduction to VHDL

The purpose of this work is to introduce VHDL to undergraduates and others having a requirement for an awareness of the language. A basic, but not extensive, knowledge of digital design is expected of the reader. Learning a foreign language requires continuous exposure to its syntax and the study of a systems hardware description language like VHDL is no different. This volume, therefore, uses the technique of repitition for the purpose of reinforcement and sound familiarity. An aim of this work is to present VHDL in a progressive manner, although it is recognized that this approach must limit flexibility towards the presentation of a fully integrated language. This is especially true in respect of the “end-of-chapter” exercises, some of which might have been more meaningful had they been able to avail themselves of aspects of the language yet to be introduced.