IC Interconnect Analysis

As integrated circuit (IC) feature sizes scaled below a quarter of a micron, thereby defining the deep submicron (DSM) era, there began a gradual shift in the impact on performance due to the metal interconnections among the active circuit components. Once viewed as merely parasitics in terms of their relevance to the overall circuit behaviour, the interconnect can now have a dominant impact on the IC area and performance. Beginning in the late 1980s there was significant research toward better modelling and characterization of the resistance, capacitance and ultimately the inductance of on-chip interconnect. This work covers the state-of-the-art methods for modelling and analyzing IC interconnect. This is done at a level suitable for most practitioners who work in the semiconductor and electronic design automation fields, but also includes significant depth for the research professionals who will ultimately extend this work into other areas and applications. “IC Interconnect Analysis” begins with an in-depth coverage of delay metrics, including the ubiquitous Elmore delay and its many variations.
This is followed by an outline of moment matching methods, calculating moments efficiently, and Krylov subspace methods for model order reduction. The final two chapters describe how to interface these reduced-order models to circuit simulators and gate-level timing analyzers respectively. This text written for CAD tool developers, IC designers and graduate students.