Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. This text describes algorithms for analyzing and optimizing the timing behaviour of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. Timing analysis and optimization techniques are described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques - retiming and clock skew optimization. This book covers the following topics: algorithms for sequential timing analysis; fast algorithms for clock skew optimization and their applications; efficient techniques for retiming large sequential circuits; coupling sequential and combinational optimizations. This book is designed for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.