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Logic Synthesis and Verification Algorithms by Gary D Hachtel
Logic Synthesis and Verification Algorithms by Gary D Hachtel
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Logic Synthesis and Verification Algorithms

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Description

This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization. Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.
Release date NZ
February 10th, 2006
Audience
  • Professional & Vocational
Country of Publication
United States
Edition
1996 ed.
Illustrations
XXXII, 564 p.
Imprint
Springer-Verlag New York Inc.
Pages
564
Publisher
Springer-Verlag New York Inc.
Dimensions
155x235x30
ISBN-13
9780387310046
Product ID
3547376

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