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High Level Synthesis of Pipelined Datapaths

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High Level Synthesis of Pipelined Datapaths by Peter Arato
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High speed digital processing and most real-time applications require dedicated chips or ASICs (Application Specific Integrated Circuits) executing specific tasks. In high level synthesis, the pipeline mode is used in the design of ASICs with increased data processing speed. Arato et al present the methods and models for solving high level synthesis problems and examine the applicability of their CAD tool, PIPE, in the context of the field towards hardware / software co-design and system level synthesis. This unique reference provides a step-by-step tutorial in "PIPE" and illustrates its applications potential, including the advantages, drawbacks and benchmark results. A supplementary CD-ROM includes synthesis subroutines and benchmarks.
Release date NZ
January 30th, 2001
Country of Publication
United Kingdom
John Wiley & Sons Ltd
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